Mar 30, 2026
The investment
The AI Gigafactory initiative is the most significant infrastructure investment the EU has ever made in artificial intelligence. With up to €20 billion in public capital at stake, it will shape European AI capability through the 2040s. The regulation governing this investment entered into force on 20 January 2026. Calls for Expressions of Interest launch in Q1 2026.
This investment must work for the European Union. It should create the conditions for European AI companies, researchers and entrepreneurs to build on publicly funded infrastructure – not merely consume it as customers of a closed ecosystem. Open standards are the mechanism that makes this possible: they ensure that the value created by public investment flows into European jobs, European intellectual property and European technological capability.
Openness is a necessary condition for this. It is not, on its own, sufficient – but does encourage and should be paired with procurement strategies that encourage supply-chain resilience. Without these, no amount of industrial policy can unlock the infrastructure for European innovation.
The problem
Open standards and interoperability have repeatedly unlocked innovation by ensuring no single vendor controls key infrastructure. Their importance extends to AI infrastructure: they are essential to an innovative, vibrant AI ecosystem in the EU.
Vendor lock-in does not principally arise from hardware. It arises from dependence on proprietary toolchains, closed software stacks and models optimised for a single backend. Increasingly, lock-in is also shifting upward to the model optimisation layer – proprietary quantisation pipelines, deployment toolchains and inference runtimes that bind users to a specific vendor’s ecosystem even when the underlying hardware appears diversified.
When the interoperability baseline is defined by one proprietary platform, that one vendor effectively controls what is interoperable. This is not a technical limitation. It is an architectural choice, and it is one that procurement criteria can and should address.
We are not calling for the exclusion of any supplier. International technology providers will rightly form part of gigafactory consortia. Our concern is narrower and more precise: the software layer – and the networking protocols that increasingly function as an extension of it.
Lock-in at the networking layer
Lock-in extends beyond compute software into interconnect infrastructure. Today, the integrated high- performance networking fabric for AI clusters – InfiniBand – is proprietary and controlled by a single vendor. This creates a secondary dependency: even where consortia might wish to diversify their accelerator hardware, proprietary networking protocols constrain that choice by requiring vendor-matched equipment across the entire cluster.
Open alternatives exist. The Ultra Ethernet Consortium is developing open, high-performance networking standards specifically designed for AI workloads, with broad industry backing. The Call for Expression of Interest should recognise networking as a critical layer where open standards are both available and necessary and should evaluate proposals on their adoption of open networking fabrics alongside open software stacks.
The economic cases for openness
The case for openness is ultimately an economic one. When publicly funded infrastructure is built on open, documented interfaces, European companies can compete to provide components, services and optimisation at every layer of the stack.
European chip designers entering the market in 2028 or 2030 can integrate their accelerators without requiring a full redesign of the software environment. European software developers can build tools, runtimes and deployment frameworks that work across the infrastructure. European cloud operators and system integrators can offer services on top of it.
Closed architectures foreclose these opportunities by design – not because European technology is inferior, but because the integration surface is controlled by a single provider. The question is not whether Europe can match every global supplier today. It is whether the infrastructure built now keeps the door open for European technologies as they mature. Open standards are what make that possible.
However, technical openness is undermined if the physical supply chain remains hyper-concentrated. If a bidder relies on a single non-domestic supplier for most of its critical components, the system remains vulnerable to external shocks regardless of the software architecture. As a result, the European Commission should also evaluate the supply-chain concentration to encourage consortia to form local partnerships.
What we ask
We call on the European Commission to require, through the Call for Expression of Interest and the Hosting Agreements, that AI Gigafactory infrastructure adopts open, non- proprietary software standards as the interoperability baseline.
This means mandating support for open standards such as ONNX, OpenXLA and SYCL; requiring that core software enabling hardware utilisation – including frameworks like PyTorch and TensorFlow, drivers, compilers and runtime libraries – is available under open-source licences; and evaluating workload-specific performance rather than synthetic benchmarks that favour architectures optimised for training over inference.
Precision by stack layer
Interoperability requirements should be defined with precision at each layer of the stack. At the orchestration, model representation and serving API layers – where tools such as Kubernetes, ONNX and Hugging Face model formats are already widely adopted – open standards are mature and enforceable, and lock-in risk is highest. At the hardware execution layer, where tightly coupled architectures deliver genuine performance advantages, requirements should focus on documented APIs at the hardware–software boundary rather than mandating full homogeneity.
This distinction strengthens rather than weakens the case: it demonstrates technical credibility and ensures that European hardware innovators can compete on performance within an open framework.
Why now
If open interoperability requirements are not embedded now, the technology stack will crystallise before future competition rules take effect. European chip designers, software developers and system integrators entering the market in 2028 or 2030 will find the door closed. The purpose of requiring open standards today is precisely to ensure that when European alternatives emerge, they can integrate seamlessly into publicly funded infrastructure.
The solution,in details
Require all consortia – regardless of whether they include technology infrastructure suppliers – to demonstrate how their architecture supports genuine multi-vendor portability at the software layer. Additionally, incorporate a “Resilience” scoring module into the evaluation:
This need not mean that every gigafactory individually deploys a heterogeneous hardware environment from day one. But the portfolio of gigafactories collectively should ensure architectural diversity, and each individual facility must demonstrate that its software stack permits the progressive integration of alternative hardware without requiring wholesale redesign.
Bids that demonstrate high resilience through reliance on onshore supply chains, multi-vendor strategy that includes EU suppliers and clear pathway for the integration of open standards, should receive a ‘Resilience’ score upgrade. By rewarding consortia that mitigate concentration, the EU can ensure that AI Gigafactories remain agile, diverse and resilient to long-term supply chain disruptions, thereby securing operational continuity through a competitive supplier base.
Score proposals on open-standard compliance, not just peak performance benchmarks. Include a specific evaluation question: how will the consortium prevent software lock-in and ensure workload portability across hardware platforms?
In the hosting agreement
Define the “enhanced conflict-of-interest safeguards” required under Article 12b(17)(h) Council Regulation (EU) 2026/150 to include binding commitments to open software interfaces, a prohibition on contractual arrangements requiring exclusive reliance on a single vendor’s proprietary software license that effectively locks out competing software or hardware providers, and documented APIs enabling third-party integration. Interpret the strategic autonomy provision in Article 12b(17)(b) to require software-layer openness as a condition for safeguarding the Union’s strategic interests.
Define the “enhanced conflict-of-interest safeguards” required under Article 12b(17)(h) to include binding commitments to open software interfaces and documented APIs. Interpret the strategic autonomy provision in Article 12b(17)(b) to require both software-layer openness and supply-chain diversification as conditions for safeguarding the Union’s strategic interests.
In evaluation and monitoring
Require annual reporting on software dependency metrics and vendor concentration to the public governance body. Assess proposals not only on current performance but on their capacity to evolve – the ability to integrate new technologies progressively, including emerging European accelerators, without requiring full hardware homogeneity from day one.
To promote transparency, each AI gigafactory Consortium should make publicly available their AI workload. For this purpose, a transparent, multi-stakeholder workload benchmark framework should be developed, covering both training and inference, designed in collaboration with European operators, AI developers and hardware providers.
Delivering long-term European prosperity
The trade-off is not performance versus diversity. A heterogeneous, open software stack requires more upfront integration work, but it delivers supply chain resilience, competitive pressure on pricing, European IP and jobs, and architectures optimised for emerging workloads. The trade-off is a short-term integration effort to deliver long-term European prosperity.
Finland’s LUMI factory already proves this is achievable: world-class AI performance on alternative hardware, using open-source software, under European control.
Europe’s AI Gigafactories will define the continent’s technological infrastructure for a generation. The decisions made in Q1 2026 will determine whether that infrastructure serves as a platform for European innovation – or as a distribution channel for technologies developed and controlled elsewhere. Open standards are how Europe ensures that its largest-ever AI investment generates returns for European businesses, European researchers and European citizens.
We urge the Commission to use the implementation instruments at its disposal to ensure that Europe’s most critical AI infrastructure investment serves European strategic interests – by requiring that the software foundations remain open, competitive and ready for the European technologies of tomorrow.
Feb 5, 2026
CTAG (Centro Tecnológico de Automoción de Galicia) and CORTUS today announced a strategic partnership aimed at advancing the development of next-generation automotive electronic control units (ECUs) based on RISC-V technology.
This collaboration combines CTAG’s extensive experience in automotive systems, vehicle development, and software integration with CORTUS’s expertise in processor architecture, including high-performance RISC-V processors, low-power and scalable AI inference for computer vision, and strong capabilities in automotive chip design. Through this partnership, the two organizations will jointly design, develop, and validate automotive ECUs using RISC-V microcontrollers (MCUs) and associated software platforms.
This collaboration will start by providing an AUTOSAR compliant MCAL and AUTOSAR support for the CORTUS Ulyss1 MCU and the development of ECUs based on this MCU ensuring interoperability and compliance with existing automotive standards. This enables OEMs and Tier-1 suppliers to retain their existing software assets and partnerships, while allowing a smooth and predictable platform transition to RISC-V and newer technologies.
The partnership will focus on aligning technical roadmaps, testing strategies, and platform requirements to accelerate time-to-market for further innovative MCUs and ECUs for automotive solutions. By combining complementary hardware and software expertise, CTAG and CORTUS aim to create long-term value and address emerging opportunities driven by software-defined vehicles, open architectures, and increasing computational demands in the automotive industry.
“This collaboration reflects our shared commitment to open and innovative technologies for the automotive sector,” said Francisco Sanchez at CTAG. “RISC-V offers new opportunities for flexibility and scalability, and partnering with CORTUS allows us to strengthen our capabilities in this rapidly evolving ecosystem.”
“We are pleased to partner with CTAG, a recognized leader in automotive systems and software integration,” said Michael Chapman at CORTUS. “Together, we aim to deliver robust, standards-compliant RISC-V automotive platforms that meet the industry’s growing performance and safety requirements.”
This strategic partnership establishes a framework for ongoing collaboration and the joint pursuit of a series of commercial automotive RISC-V solutions.
For media inquiries, please contact:
Mr. Duc Nguyen Huu| duc.nguyen.huu@cortus.com
Cortus S.A.S.| Website: www.cortus.com
About Cortus:
Cortus is a global fabless semiconductor company delivering high-performance RISC-V automotive chips up to 4 GHz capable of 4 instructions/cycle, with integrated AI inference optimized for computer vision. Cortus designs and supplies advanced RISC-V chips tailored for automotive, avionics, and AI-driven systems, combining high performance, energy efficiency, and functional safety to meet the most demanding industry requirements. Visit us at https://www.cortus.com
About CTAG:
CTAG is an automotive technology center specializing in vehicle development, advanced mobility solutions, and software development. With strong expertise in automotive systems, electronics, and software integration, CTAG supports OEMs, Tier-1 suppliers, and mobility stakeholders in the development and validation of innovative, safe, and sustainable automotive technologies. Visit us at https://www.ctag.com
Oct 30, 2025
General description
Cortus is at the forefront of edge-cutting AI inference chiplet development. We are seeking a Senior Digital IC Design Engineer (m/f) to join our R&D Center of Excellence in Mauguio and strengthen our on-site hardware design team.
Role Overview
As a Senior Digital IC Engineer, you will be a key contributor and technical lead in the design and development of complex digital integrated circuits (ICs), including System-on-Chip (SoC) and IP cores for AI accelerators. You will also lead the AI accelerator branch, managing and mentoring the engineering team.
Key Responsibilities
- Lead the design, implementation, and verification of digital ICs for AI inference accelerators.
- Manage the engineering team, providing guidance and technical support.
- Participate in all phases of the ASIC/IC development lifecycle, from specification to tape-out.
- Collaborate closely with cross-functional teams, ensuring high-quality and timely delivery.
Minimum requirements
- Education: PhD in Computer Science, Electronics, or Engineering, or MSc in Computer Science/Electronics, or equivalent.
- Experience: Deep experience in defining IPs, CPU architecture, and digital IC implementation.
- Technical Skills:
- Knowledge of configuration database management (Git, SVN).
- Scheduling and reporting activities.
- Language: Proficient in English, both written and spoken.
- Professional Skills:
- Proven communication and interpersonal skills.
- Ability to assume responsibility for a variety of technical tasks and troubleshooting.
- Strong sense of responsibility and ability to meet deadlines.
Candidates with higher educational degree (PhD) and/or extensive professional experience involving similar requirements are strongly exhorted to apply since the related skills will be strongly taken into account within the fast-growing context of the CORTUS’ organization.
Highly preferred skills
Architecture & Computation Knowledge:
- Familiarity with AI/ML hardware accelerators or neural network architectures (e.g., CNNs, ViTs).
- Exposure to AI/ML frameworks (e.g., TensorFlow, PyTorch).
- Knowledge of floating-point formats: FP32, FP16, FP8, FP4.
- Understanding of floating-point operators.
- Experience with SIMD computing units and tensor processing units.
- Awareness of performance bottlenecks in AI workloads on embedded hardware.
Job type and locations
- Employment Type: Full-time, permanent contract.
- Primary Location: Mauguio, Hérault, France.
Application Reference
Application reference: FR-MP-291025-DIG-AI
Benefits of working at CORTUS
This position is intended for mid-level engineers (higher levels will be considered for the ideal candidate) and comes with an attractive compensation package, including:
- Competitive salary
- Meal card and comprehensive health and care insurance
- A culture that values collaboration, teamwork, and recognition, accomplishments are duly celebrated
At CORTUS, we believe in creating an environment where innovation thrives, and where every team member can contribute meaningfully to next-generation technology.
Additional information
CORTUS is committed to fostering a diverse and inclusive workplace and welcomes applications from candidates eager to join an environment that encourages initiative, flexibility, and creativity.
Successful candidates will join a team of highly experienced engineers and innovators working passionately across a wide range of technologies from silicon chip design to cloud-based software interfaces.
We promote transparency and open communication through regular Q&A sessions with the executive team, and support a healthy work-life balance with an open time-off policy and a culture of mutual respect and trust.
Oct 16, 2025
Bangalore/Mysuru, India & Montpellier, France, ChipSync, a leading innovator in Connected Car Technology in India and Cortus, a global fabless semiconductor leader specializing in RISC-V chips and AI inference chiplets, are proud to announce a strategic collaboration to jointly develop next-generation electronic automotive and consumer solutions tailored for the Indian market.
This partnership aims to redefine the future of automotive and software-defined vehicle (SDV) technologies by integrating Cortus’ cutting-edge RISC-V automotive chips and AI chiplets for computer vision with ChipSync’s expertise in connected car software solutions.
Empowering India’s Automotive Sector with RISC-V Innovation
Together, Cortus and ChipSync are poised to deliver transformative automotive and consumer electronics platforms that will accelerate the adoption of standard, scalable, and high-performance solutions in India’s rapidly evolving automotive landscape.
“This partnership marks a pivotal moment in our journey to bring next-gen connected vehicle solutions to the Indian market,” said Hariprasad KB, CEO at ChipSync. “Combining our software excellence with Cortus’ world-class silicon and chiplet technologies allows us to offer more intelligent, flexible and cost-effective platforms.”
“India is a one of key markets for RISC-V adoption, and this collaboration underscores our commitment to democratizing high-performance computing in automotive and beyond,” added Michael Chapman, CEO of Cortus. “We are excited to work with ChipSync to deliver secure and AI-driven solutions for the vehicles of tomorrow.”
Driving the Future – Together
As India accelerates toward becoming a global automotive innovation hub, this partnership aims to play a pivotal role in strengthening the RISC-V ecosystem, enabling faster development cycles, AI-driven safety features and energy-efficient designs tailored to OEM demands.
About ChipSync Technologies Pvt, Ltd:
ChipSync is a technology company experienced in building high quality software products and solutions for automakers and consumers across the world. ChipSync expertise in automotive software development with primary focus on in-vehicle infotainment, connected car technology and security. Our solutions have been deployed in over millions of cars across the world. Visit us at https://www.chipsynctech.com
About Cortus S.A.S:
Cortus is a global fabless semiconductor company delivering high-performance RISC-V automotive chips up to 4 GHz capable of 4 instructions/cycle, with integrated AI inference optimized for computer vision. Cortus designs and supplies advanced RISC-V chips tailored for automotive, avionics, and AI- driven systems, combining high performance, efficiency, and functional safety to meet the most demanding industry requirements. Visit us at https://www.cortus.com.
For media inquiries, please contact:
- ChipSync, Hari: hari@chipsynctech.com
- Cortus, Jay Park: jay.park@cortus.com
Oct 6, 2025
In a historic breakthrough for the global tech industry, the eProcessor Project proudly announces the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. This innovative processor, manufactured in a 22nm process, represents a leap forward in computational performance, setting a new benchmark for efficiency and speed in a range of industries, including automotive, AI, and high-performance computing.
Out-of-order execution allows the processor to optimize the use of system resources by executing instructions out of sequence. This greatly enhances the processor’s overall performance, offering substantial gains for applications that require high computational power. Moreover, the processor runs Linux, demonstrating its full functionality for real-world applications and confirming its capabilities in complex environments.
A Landmark Achievement for RISC-V and European Innovation
This pioneering development positions Europe as a leader in the global semiconductor and open-source hardware movement. The eProcessor Project, which brings together a collaborative network of industry experts, innovators, and researchers including key partners like Chalmers University, Forth, Barcelona Supercomputing Center (BSC), Christmann, Exapsys, Extoll, Sapienza, Thales, Universität Bielefeld, and Cortus, marks a significant milestone in the RISC-V ecosystem. As the main partner contributor on the RISC-V processor, Cortus played a critical role in the architecture, design, and development of the 4-way Out-of-Order (OoO) RISC-V processor, driving the project forward with its deep expertise in processor architecture. Cortus’ contributions were pivotal in realizing the ambitious goals of the project, ensuring that the processor met the highest standards of performance, scalability, and energy efficiency.
Cortus was also responsible for the silicon implementation and chip packaging.
This project is fully aligned with Cortus’ strategy and roadmap, reinforcing the company’s commitment to advancing RISC-V architecture and driving innovations in the semiconductor space, particularly in areas like high-performance computing, and automotive solutions.
Key Milestone: Europe’s First Out-of-Order RISC-V Processor Silicon Successfully Deployed
The successful deployment of the Europe’s first out-of-order RISC-V processor silicon marks a key milestone in the eProcessor Project. This achievement represents the culmination of years of collaboration and technological innovation, bringing Europe to the forefront of semiconductor advancements. This milestone opens the door for future generations of processors, driving progress in both high-performance computing (HPC) and automotive systems, and will enable the development of a full-stack RISC-V ecosystem.
In Line with the EU Strategy and the European Chips Act
This project is a key step forward in Europe’s broader technological goals and is fully in line with the European Union’s strategy for semiconductor innovation, especially in light of the EU Chips Act. The EU has committed to boosting its semiconductor capacity, and the eProcessor Project plays a critical role in advancing Europe’s position in the global chip market. By contributing to the development of open-source RISC-V processors, the project supports the EU’s vision for technological autonomy, innovation, and a more resilient semiconductor supply chain across Europe.
eProcessor Project Lead, Lluc Alvarez, from BSC, commented: “The successful development of the first out-of-order RISC-V processor is a true testament to the power of collaboration and innovation. By leveraging the strength of our talented project members, including Cortus as the primary contributor, we’ve made a quantum leap in RISC-V processing technology, setting the stage for a new generation of computing solutions. This project is a critical milestone in Cortus’ strategic roadmap and reinforces our position at the forefront of RISC-V development.”
During the final deliverables and closing meeting of the eProcessor project, it was highlighted that the project has not only met its technical objectives but has also exceeded expectations. The out-of-order RISC-V processor is a significant milestone, showcasing the strength of Europe’s innovation ecosystem and suggesting the potential for a new era in computing.
Revolutionizing the Automotive Industry and Beyond
The successful creation of this out-of-order RISC-V processor is poised to revolutionize a number of industries, especially the automotive sector, where computing power and efficiency are critical to the development of autonomous driving systems, vehicle safety, and intelligent transportation. The processor’s ability to deliver high-performance computing at a lower energy cost is especially valuable in embedded systems, where resource efficiency is paramount.
Building a Complete European Open-Source Ecosystem
The eProcessor Project built a new Out-of-Order (OoO) RISC-V processor and accelerators to deliver a complete European full-stack ecosystem. The technology developed is extendable, energy-efficient (low power), extreme-scale (high performance), and suitable for uses in both high-performance computing (HPC) and embedded applications. Moreover, it is extensible, enabling easy integration of on-chip and/or off-chip components to meet evolving needs.
The project is an ambitious combination of processor design based on the RISC-V Instruction Set Architecture (ISA), applications, and system software. It leverages and extends pre-existing Intellectual Property (IP) combined with new IP that can be used as building blocks for future HPC systems and embedded devices, further solidifying Europe’s position as a leader in open hardware development.
Collaborative Effort with Leading Research Institutions and Industry Experts
The eProcessor Project’s success owes much to the collaboration with leading research institutions and industry experts. Partners like Chalmers University, Forth, BSC, Christmann, Exapsys, Extoll, Sapienza, Thales, Universität Bielefeld, and Cortus have contributed their expertise in hardware design, software optimization, and high-performance computing to ensure that the processor meets the demands of modern computing environments. These partnerships have been integral in validating the processor’s ability to run complex software, including Linux, making it ready for a wide range of real-Europe applications.
Global Impact and the Future of RISC-V
This processor not only represents a significant step forward in RISC-V adoption but also pushes the boundaries of what is possible with open-source hardware. With its enhanced performance and scalability, this breakthrough out-of-order processor is expected to fuel innovation in fields ranging from AI and machine learning to edge computing and smart devices.
As RISC-V continues to gain traction globally, this achievement helps cement the eProcessor Project’s role in the ongoing transformation of the semiconductor industry, offering an alternative to traditional closed-source architectures and providing new opportunities for companies to innovate with flexible, customizable processors.
The Path Ahead: Unlocking New Potential
To fully realize the potential of this groundbreaking RISC-V processor and compete at a global level, continued investment and strategic support are essential. While the eProcessor Project has made significant progress, further funding is necessary to enhance performance, refine architecture, and position it as a competitor to industry leaders like AMD, Intel and Arm.
This project is more than just a technical achievement, it’s a real opportunity to foster a new European hardware ecosystem, advancing technological autonomy and reducing reliance on external suppliers. With additional resources, the eProcessor Project can drive innovation in key sectors such as HPC, AI, automotive, and IoT, contributing to Europe’s long-term goals of digital sovereignty and leadership in semiconductor design.
Investing in the eProcessor Project not only supports cutting-edge technology but also positions Europe as a global leader in sustainable, customizable processors. With the right funding, this initiative will unlock new economic and technological opportunities, advancing Europe’s competitive edge in the global market.
About the eProcessor Project:
The eProcessor Project is a collaborative effort between leading tech innovators, academic researchers, and industry experts, including key contributors such as Chalmers University of Technology, Forth, Barcelona Supercomputing Center (BSC), Christmann, Exapsys, Extoll, Sapienza, Thales, Universität Bielefeld, and Cortus. Focused on the development of RISC-V processors, the project aims to push the boundaries, delivering high-performance, customizable computing solutions for applications in automotive, AI, IoT, and more. With a commitment to fostering global innovation, the eProcessor Project continues to shape the future of semiconductor design, building a European ecosystem.
For media inquiries, please contact:
- BSC, Lluc Alvarez: eprocessor-general@bsc.es
- Cortus, Christophe Genevois: christophe.genevois@cortus.com
