Cortus

CAREERS

Digital verification engineer

General description and main responsibilities

CORTUS is working on the next generation of IoT connectivity modems building up 5G massive Machine Type Communication (mMTC) chipset that will define ultralow power, high reliability and lowcost benchmarks for SoC products.
To become a chip leader in wireless connectivity for the IoT market, we are looking for Mid/Senior Digital Verification Engineers (m/f) for our R&D centers of excellence.

The candidate must have a background in digital electronic design with at least 5+ years of experience in design and verification languages (Verilog, SystemVerilog), methodologies (Formal, UVM) and well knowledged of the entire VLSI flow.

The candidate will be well versed with verification methodology and create verification plan as well as test bench architecture to run digital and toplevel simulations using state of the art EDA tools.

He/She will directly interact with system architects, Digital design team, AMS design teams to lead the verification flows of the CORTUS’ SoC family product for wireless connectivity.

The ideal applicants should be familiar on working in a multicultural environment and with teams spread over several sites.

Minimum requirements

Engineering Msc. or Bsc. degree in Electronics/Telecommunications/Computer Science or equivalent;
Good understanding of the standards NBIoT, BLE and IEEE 802.15.4

Deep experience in defining IPs test specification in closed collaboration with product definers and architects;

Strong experience on digital verification methodologies (Formal and UVM) using state of the art EDA tools;

Understand and debug digital RTL;

Determine technology requirements, dependencies and deliverables based on project specifications;

Experience in writing IP verification plans, creating test benches and automating regression test suites to ensure 100% coverage prior tapeout;
Experience with mixed signal (analog, digital) verification methodologies using state of the art EDA tools;

Capability in developing behavioral models for analog IPs, understand and debug analog schematics;

Knowledge of Design For Testability (DFT) techniques;

Knowledge in configuration database management (Git, SVN);

Scheduling and reporting activities;

English language written and spoken;

Proven communication/interpersonal skills;

Able to assume responsibility for a variety of technical tasks and troubleshooting;

Strong sense of responsibility and ability to achieve deadlines.

Highly preferred skills (plus)

Basic Experience with RISKV ISA;
Basic Experience in Digital Signal Processing (DSP)

Software development using C/C++;

Script programming language (e.g. perl, shell, phyton);
Familiar with realtime embedded software (especially debugging).

Job type, primary locations and application reference

Full time with permanent contract

Primary locations: LECCE, (Apulia region), Italy

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Office

491 rue Charles Nungesser
Bâtiment Télécom II
34130 MAUGUIO
FRANCE

Phone Number

+33 4.30.96.70.00

VAT Nº FR 43 484 893 763

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