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RISC-V PROCESSOR

RISC-V PROCESSOR

Cortus is a Platinum Founding Member of the RISC-V Foundation

RISC-V combines a modular technical approach with an open, royalty-free ISA. Using an open source solution, it provides flexibility, design freedom and support open architecture extensions to the RISC-V ISA.

Cortus developments are based on cost-effective RISC-V SoC using its own extensive IP portfolio for 32-bit to 64-bit core chips for the following fields:

  • NCortus CIoT25, sub-1 GHz chipset
  • NCortus C 200, NB-IoT chipset
  • NCortus Lotus 1, Microcontroller chipset for general purpose application
  • NCortus Lotus 2, Microcontroller chipset for the Automotive market
  • NeProcessor: a new 64-bit generation for High Performance Computing (HPC)

This HPC implements the RISC-V 64-bit instruction set architecture. This offers numerous advantages compared to the common CISC architecture implemented by Intel and AMD. In RISC-V the large number of compiler visible register names combined with a load/store architecture and absence of memory to memory operations means many fewer memory operations are required. Exploiting the RISC-V Weak Memory Ordering model in conjunction with fewer memory operations allows dynamic execution optimizations which otherwise would not be possible within a Total Store Order approach. This allows a RISC-V processor to surpass Intel/AMD in Instructions Per Cycle (IPC). Further, optimized implementations of atomic memory operations in conjunction with the cache hierarchy improves the performance of multi-threaded applications such as those which run on a large scale HPC system.

Cortus offers a comprehensive ecosystem including IDE, compilers, assembler, linker, debugger and trace (supporting profiling and MC/DC for safety certifications) all of which have been carefully tested and integrated delivering significant value to Cortus’ strategic partners and customers.

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