Back-end engineer

General description and main responsibilities

Cortus is working on next generation IoT connectivity modems building up 5G massive Machine Type Communication (mMTC) chipset that will define ultralow power, high reliability and lowcost benchmarks for SoC products that rely on NBIoT, BLE and IEEE 802.15.4.To become a chip leader in wireless connectivity for the IoT market, we are looking for Mid/senior Radio Frequency Design engineers by 2022 in order to strengthen our onsite team.
The candidate must have a solid background in RF microelectronic with at least 3+ years of experience in Radio Frequency IC design.

As a Radio Frequency Ic designer, the candidate will specify, design, layout and test Radio frequency (e.g. PA, LNA/LNTA, mixer, HF oscillators, LO driver, VGA and TIA blocks in deep submicron CMOS technology) directly interacting with system architects, Digital design team, AMS design teams and test engineers for the integration of the RF functions into the CORTUs’ SoC family product for wireless connectivity.

The ideal applicants should be familiar on working in a multicultural environment and with teams spread overs several sites.

Minimum requirements

Engineering Msc. or Bsc. degree in Electronics/Telecommunications or equivalent;
Direct tapeout experience in design and test of one or more of the following RF blocks: PA, LNA, mixer, HF oscillators, LO driver, VGA and TIA;
Experience in Power Management architecture typologies, such as PWM control, constantontime control, and voltage/current mode controls

Capability to handle the design of CMOS/BCD power management circuits (nuck, boost, LDOs, bandgaps, bias, comparators, and opamps) with main EDA tools and meeting performance, area, power and speed constraints

Capability to review and provide feedback for Printed Circuit Board design from a power perspective and associated I/O

Knowledge of physical construction and characteristics of capacitor and inductors (onchip and offchip)

Knowledge of LatchUp and ESD phenomena to assure the functional security of the system

English language written and spoken

Highly preferred skills (plus)

Engineering Msc. or Bsc. degree in Electronics/Telecommunications or equivalent;
Good understanding of the standards NBIoT, BLE and IEEE 802.15.4

Deep experience in translating schematics to mask Layouts
Experience with all aspects of physical ASIC/SoC integration including floorplanning, clock and power distribution, global signal planning, I/O planning and hard IP integration;

Experience with layout implementation criticalities (e.g. matching, electromigration, LatchUp and ESD);
Capability to handle main Physical Design Verification flow steps performing LVS, DRC, ERC, and all required verifications with and corresponding main EDA tools;
Capability to handle toplevel layout integration tapeout process, which involves generation of bond diagram/RDL, final clean GDS database and proper documentation;
Knowledge about AnalogOnTop and DigitalOnTop approach and methodologies, P&R flow steps;

Scheduling and reporting activities;

English language written and spoken;

Proven communication/interpersonal skills;

Able to assume responsibility for a variety of technical tasks and troubleshooting;

Strong sense of responsibility and ability to achieve deadlines.

Job type, primary locations and application reference

Full time with permanent contract
Primary locations: LECCE, (Apulia region), Italy

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Phone Number


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